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# Chapter 7 - Memory and Bistables

## Feedback equals memory

So far the only circuits that we have looked at have been feed-forward, i.e. the inputs feed through to the outputs with no signal looping back on itself. Even the binary adder which you met in Chapter 3 was a feed-forward network, even though it looked as though the inputs were feeding back on themselves - in fact, the inputs were merely "staggered."

Feedback is a completely different kettle of fish, however! With feedback, the outputs of the circuit are used to control the same inputs that generated them in the first place. Here is an example of what is probably the simplest feedback circuit:

 In order to calculate the output of the AND gate we have to make some assumption about what the output is already and follow it to its logical conclusion. For instance, let's suppose the output and the input are both 1. In that case the system is stable - the output feeds back to the AND gate so that it has two 1 inputs, which sustains the output as 1. Everyone's happy.

 Now let's assume that the output remains at 1 and that the input goes to 0. Suddenly the AND gate is in an unstable state! Its inputs are 1 and 0, which should produce an output of 0, and yet the output finds itself as 1. As quick as a flash, the output goes to 0 to match this. Now the AND gate is in another stable state, with both its inputs 0 and its output at 0. Again everyone is happy (Well I certainly am!)

 What happens if we take the input back to 1 again? Well, the output is at 0 and this feeds back as one of the inputs to the AND gate. Although the input is 1, the AND gate can no longer produce a 1 output, and the output remains at 0. This is another stable state, with the input at 1 and the output at 0.

Essentially, the AND gate starts off in a stable state, with the input and output both at 1. As soon as we drop the input to 0, the output of the AND gate goes to 0 and remains there whatever we do with the input. Essentially the AND gate has remembered the fact that the input once went to 0, and has never forgiven us for it! The use of feedback has given the circuit a simple memory. I have summarised the behaviour of the circuit in the truthtable below:

 Input Assumed state of output New state of output 0 0 0 0 1 Unstable! (Goes to 0) 1 0 0 1 1 1

In fact, the textbooks have a different way of representing this. They call the output at any particular instance Qn where n represents the particular instance. Using this notation, the output at the very next instant of time (the next "second", if you like, although logic gates take a miniscule fraction of a second to react) would be Qn+1. Now we can simplify the table:

 Input Qn+1 0 0 1 Qn

This means that if the input is 0, then the output of the circuit is 0. If the input is 1 then the output is the same as it was one instant ago. If it was 0 then it stays as 0. If it was 1 then it stays as 1.

Such a simple circuit would not be used as a proper memory element. For a start, how would you ensure that the output of the circuit was 1 to begin with? You would have to connect the AND gate up so as to produce a 1 and then rewire the circuit without losing that output. Yuk! Secondly, once the AND gate has "shot its bolt" then it has no further processing to do. The only situation where you might want to use it is if you want to detect whether an event has happened. For instance, you could connect the input to a door such that opening the door breaks the circuit. The output of the AND gate would tell you whether the door had been opened or not.

Of course, you could substitute other gates instead of the AND gate. What would happen if you replaced it with an OR gate, a NAND gate, or a NOR gate? I will leave you work these out for yourselves.

## The R-S Bistable

Now for a more practical circuit. This is the first of several circuits, all of which are based around this design, which form the basis of real memory elements. The RS-bistable (also known as a flip-flop) has the following basic structure:

(It can also be constructed from NOR gates in a similar pattern. I will stick to the NAND gate version as it is more common). As you can imagine, since this circuit has two feedback connections, its logic is quite complicated. To work out what its stable states are, we need to consider not only what its true inputs are (which are traditionally called R and S for reasons which I will explain later) and also what the current state of the outputs are.

The textbooks always refer to the outputs as Q and . This is because, apart from one situation, they are always the opposite of each other. Again, the current states of the outputs are called Qn and n, and the next state of the outputs we will refer to as Qn+1 and n+1.

To calculate the behaviour of this circuit, we need to draw up a truthtable like this:

 R S Qn n Qn+1 n+1 0 0 0 0 ? ? 0 0 0 1 ? ? 0 0 1 0 ? ? 0 0 1 1 ? ? etc.

I have carefully avoided filling in the outputs, as I thought you should do that for yourself. However, let's deal with a few of them so you can see the pattern. Firstly, let's consider the case when R = S = Qn = n = 0.

Ah, but wait a minute! Surely if both the outputs are 0 then all the inputs to the NAND gates are 0 so they can't be producing 0 outputs in the first place! That's right (well done you!), and this is an unstable state (an impossible state). If the circuit did for some reason find itself in this state, it would immediately change to something more stable. For this reason, we can eliminate the line where R = S = Qn = n = 0 from the truthtable.

In fact, the only stable configuration of the circuit when R = S = 0 occurs when both the outputs are 1, i.e. R = S = 0, Qn = n = 1:

This is the stable configuration that the circuit would move into if ever it found itself with R = S = Qn = n = 0.

As you work through all 16 lines of the truthtable, you will find that you can eliminate all of them except 5. The 5 stable configurations occur when Qn = Qn+1 and n = n+1. Here is the severely pruned table:

 R S Qn n Qn+1 n+1 0 0 1 1 1 1 0 1 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1

Again, the textbooks put it slightly differently. They also give names to the states:

 R S Qn+1 n+1 Name of state 0 0 1 1 (not generally used) 0 1 1 0 Set 1 0 0 1 Reset 1 1 Qn n Hold

So, putting S = 1, R = 0 sets the value of Q (and clears the value of ). This is why input S is called that - it stands for "Set". Similarly, putting S = 0, R = 1 clears the value of Q (and sets the value of ). This is the reason that input R is called that - it stands for "Reset".

The interesting state is when S = R = 1, referred to as the "Hold" or "Latch" state. In this case, the outputs retain the same state that they had before. This is the memory element of this particular circuit. The circuit is more practical than the simple single-gate versions that you saw above - it has a way of setting the value held to 1, a way of clearing it to 0, and a way of holding whichever value has been stored in it.

The way this circuit would be used in practice is that both S and R would be held at 1. When you wanted to set the output Q to 1 (we can discount the output as that is always the opposite of Q except in the state that is not generally used), you drop the R input to 0. Then you can return it to 1 (i.e. S = R = 1 again) and the circuit will keep its new state. When you want to clear the output Q to 0, simply drop the S input to 0, and return it to 1 again. The circuit switches over and then stays in its new state. We say that the circuit flip-flops from one stable state to the other. It has two stable states, hence the name "bistable".

Try clicking the mouse on the Set and Reset rectangles in the diagram below, to see this effect for yourself:

## A point of confusion

We have to be careful here. Some textbooks mark the inputs the other way round. They hold that the inputs are kept at 1 normally, and only drop to 0 when they are activated, i.e. the Set input is dropped to 0 to set the Q output to 1, and returned to 1 afterwards. The Reset input is dropped to 0 to clear the Q output to 0, and returned to 1 afterwards. Don't be surprised if you see in textbooks the Q output on the same "side" of the circuit as the Set input:

## Races

Signals take time to travel through circuits. Although electrons, the charged particles which carry electric signals, can start and stop in the order of nanoseconds (i.e. within billionths of a second), the fact that this is not instantaneous can still cause problems. Specifically, we can have two digital signals racing each other down different wires and causing some erroneous result. Take a look at this circuit:

Here we have a device called a clock which provides a regular "heartbeat" signal, altering from 0 to 1 and vice-versa at regular intervals (more on this in the next section). This signal is passed into an AND gate. The other input to the AND gate is the same signal inverted, i.e. when the clock produces a 1 output, the AND gate gets the inputs 1 and 0, and when the clock produces a 0 output, the AND gate gets the signals 0 and 1.

Theoretically, the output from the AND gate should always be 0 simply because its inputs are always different. However, if we measure the actual output coming from the AND gate, we find that it really is 0, apart from tiny spikes which occur when the clock changes state from 0 to 1. A spike is a change in the signal lasting a fraction of a millionth of a second, equivalent to a needle that flickers on a scientific instrument before going back to what it read before (only a lot faster).

The spike occurs because the signal that passes through the inverter takes slightly longer than the one that hits the AND gate directly. For that tiny fraction of a second when the direct signal has just gone to 1, the inverted signal is also 1 as the inverter struggles to catch up, and the AND gate produces a 1 output.

We need an instrument called an oscilloscope to detect the presence of these spikes since they happen so quickly. But the circuit can detect them easily enough! Here we have the same circuit again, this time connected to a single-shot OR memory element (a variation of the single-shot AND gate that you saw in the first section). The OR gate is set so that its output is in a stable 0 state. Click on the button when you want the clock to start ticking!

As soon as the clock starts ticking the AND gate starts producing a series of spikes. One spike is all it takes to activate the OR gate and send its output to 1, and due to the feedback connections of the OR gate, the output then stays at 1 for ever.

## Clocked Circuits

The circuits that we have been looking at so far (up to the section on races, at least), including the R-S flipflop, are termed asynchronous. This means that they respond to changes to their inputs as soon as those changes occur. However, as you have seen, that can prove disastrous, due to the presence of races in the circuit. What we want is for a nice steady circuit where the signals only change at predictable intervals. For this reason, we use a clocked circuit.

A clock provides a regular drumbeat that is followed by all the parts of a synchronous circuit. We have to ensure that all the signals change only at one specified point in every beat of the clock. In practice, this means either that the signals change when the clock goes from 0 to 1 (termed the "leading edge" of the clock pulse) or when the clock goes from 1 to 0 (termed the "falling edge" or "trailing edge" of the clock pulse). The signals never change when the clock holds a steady value (either 0 or 1). Basically, leading-edge circuits all change when the clock goes "tick", trailing-edge circuits all change when the clock goes "tock".

The version of the R-S flip-flop that you saw before is asynchronous - as soon as you alter one of the inputs, it reacts, completely ignoring any clock pulse that might be around. Let's produce a variation on it that only works when the clock pulse goes "tick".

Now we have the textbook tradition turned on its head. Remember, according to the text books, the inputs to the memory part of the flip-flop are activated by dropping them down to 0, then returning them to 1 so that the status of the flip-flop is frozen. However, the NAND gates in front of the memory element reverse this. Providing the clock signal is 1 (see below), a signal of 0 on the Set input will be turned into a 1 signal when it passes through the initial NAND gate. Similarly, the reset signal will normally be 0 (causing a 1 signal to be passed to the memory element) and you will take it up to 1 in order for the signal to the memory element to drop to 0.

This means, effectively, that the "hold" position for this clocked flip-flop should be R = S = 0, rather than R = S = 1. You will raise either Set to 1 temporarily in order to set the Q output, or Reset to 1 temporarily in order to clear the Q output. This is best understood by trying it out on the circuit above.

However, the Set and Reset inputs will only work when the Clock input is at 1. If you click on Clock so that it goes to 0, then the state of the flip-flop is fixed because the Set and Reset signals don't make it past the first set of NAND gates. Try it and see! It's like being faced by a set of traffic lights set at red. Clicking on the Clock input so that it goes to 1, and the traffic lights turn green. The NAND gates become "transparent", and the R-S flip-flop works exactly as it did before.

We use the following symbol to represent a clocked R-S flip-flop:

or

## The Master-Slave Circuit

The clocked circuit is an improvement on the simple R-S flip-flop, but we have only solved half the problem. When the clock signal goes high, the flip-flop becomes transparent and any signal affects it immediately. However, we can piggy-back two clocked R-S flip-flops end-to-end to solve the rest of the problem:

The clock signal is provided to both the clocked flip-flops, but it is inverted before being fed into the second one. This means that when the clock signal for the first flip-flop is 1, it is 0 for the second one, and vice-versa. Effectively, this set-up gives two sets of traffic lights, where one of them is red and the other is green - they are never the same colour at the same time.

The final output of the circuit only appears at the far end of the master-slave flip-flop when the clock goes to 0 (this is when the "slave" part of the circuit is activated). The clock pulse going from 1 to 0 is referred to as the "trailing edge", and we say that this circuit is "trailing edge triggered".

The part of the clock cycle where the signal goes from 0 to 1 is referred to as the "Leading" edge or "Rising" edge. We can alter the master-slave flip-flop so that the final signal appears when the clock goes from 0 to 1:

In this case, we would say that the circuit was "leading edge triggered" or "rising edge triggered".

## The D-Latch

A variation of the clocked R-S flipflop is the Data Latch, or D-Latch. This is a form which is more convenient to use in some cases as it only has one input. In this case, the single input (which is called D) is fed to the Set input. D is also inverted and sent to the Reset input as in the following diagram:

In this case, if D is 1 then it is equivalent to the Set condition of the previous flip-flop (i.e. S = 1 and R = 0, which sets the output Q to 1 and clears the output to 0). Similarly, if D is 0, then it is equivalent to the Reset condition of the previous flip-flop (i.e. S = 0 and R = 1, which clears Q to 0 and sets the output to 1).

Of course, all this only happens when the clock input is 1. Whenever the clock input is 0, the entire state of the circuit beyond the first pair of NAND gates is frozen in whatever position it was in when the clock pulse dropped to 0. There is nothing, however, to stop us making a master-slave version of the D-Latch that has all the same advantages as the master-slave version of the R-S flip-flop.

 The master-slave D-latch would be represented in a similar way to the master-slave R-S flip-flop. Since the output is always the opposite of the Q output, we are often too lazy to draw it. On the right I have shown how 8 D-latches can be wired together to form a simple 4-bit register. Again, the circuit is trailing-edge triggered, so that when the clock pulse goes to 1, the 4-bit pattern on the input is latched into the master part of the register. Then, when the clock falls to 0, the signal is latched into the slave side of the register and becomes visible at the outputs.

## The J-K Flip-flop

There is one more improvement to the RS flip-flop that we can make. Up to now, I have stated that there is one state of the flip-flop that is not generally used. In the simple R-S flip-flop (the unclocked version), this occurs when R = S = 0. However, as soon as you add a clock pulse, then the inputs are both 1 for the unused state.

Wouldn't it be good if we could put this state to good use! Well, we can turn it into a toggle state. The word "toggle" means that the flip-flop changes its state from 1 to 0 or from 0 to 1 in time with the clock pulse.

 This diagram shows the J-K flip-flop which is an adaptation of the R-S flip-flop. It can also take the form of a master-slave circuit. However, there is additional feedback. The two AND gates at the input to the S-R flip-flop prevent both S and R being 1 at the same time. The truthtable for the JK flip-flop is shown below:

 J K Qn+1 Name of state 0 0 Qn Hold 0 1 0 Reset 1 0 1 Set 1 1 n Toggle

In this case, I haven't bothered with the n+1 output as that is now always the opposite of the Qn output.

The J-K flip-flop does exactly what its R-S equivalent does, except for the special case when J = K = 1 (the "Toggle" state). In this case, the output of the circuit always switches to the opposite of its current state whenever the clock pulse goes from 0 to 1 (the circuit is leading-edge triggered). This behaviour is often shown in the form of the following diagram, which shows the clock pulse in the upper part and the Qn output in the lower part:

You can see from the diagram that the output of the circuit has the same basic shape as the input, but only changes half as frequently. Effectively, the circuit has operated as a "frequency halver". Often the output is then fed into another J-K flip-flop that halves the frequency again. in this way, a chain of J-K flip-flops can be wired together to form, what is in effect, a binary counter: